The present invention relates to electronic circuits, and more particularly to locking and unlocking of data to a reference clock signal in a clock and data recovery system.
The increasing speed with which multiple types of data, such as text, audio and video, are transported over existing communication networks has brought to the fore the reliability with which such data transportation is carried out. In accordance with one conventional method, to ensure reliable data transfer, the data is first encoded with a reference clock signal at the transmitting end of the network to generate a composite signal. Thereafter, the composite signal is transmitted over the network to the receiving end. At the receiving end, the data and clock signals are recovered from the composite signal to ensure that the data and clock signals remain synchronous with respect to each other.
The clock and data recovery is typically carried out, for example, by a delay locked loop or a phase locked loop. In operation, a phase locked loop maintains a fixed relationship between the phase and frequency of the signal it receives and those of the signal it generates. FIG. 1 is a simplified block diagram of a conventional phase locked loop (PLL) 10 adapted to maintain a fixed relationship between the phase and frequency of signal CLK and signal Vref. PLL 10 includes, among other components, phase detector 12, charge pump 14, loop filter 16 and voltage controlled oscillator (VCO) 18. The extracted clock signal Clk is supplied at the output terminal of VCO 18. Once in a locked state, the phase and frequency of signal Clk generated by PLL 10 is locked to those of signal Vref received by PLL 10. The operation of PLL 10 is described further below.
Phase detector 12 receives signals Vref and Clk, and in response, generates signal A that corresponds to the difference between the phases of these two signals. Charge pump 14 receives signal A and in response generates current signal I whose magnitude varies depending on the magnitude of signal A. Loop filter 16 filters out the high frequency components of signal I and delivers the filtered-out signal to VCO 18.
If signal Vref leads signal Clk in phase—indicating that the VCO is running relatively slowly—signal A causes charge pump 14 to increase its output current I until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal Vref. If, on the other hand, signal Vref lags signal Clk in phase—indicating that the VCO is running relatively fast—signal A causes charge pump 14 to reduce its output current I until VCO 18 achieves an oscillation frequency at which signal Clk is frequency-locked and phase-locked with signal Vref Signal Clk is considered to be locked to signal Vref if its frequency is within a predetermined frequency range of signal Vref. Signal Clk is considered to be out-of-lock with signal Vref if its frequency is outside the predetermined frequency range of signal Vref.
FIG. 2 is a schematic block diagram of a lock-detect circuitry 20 adapted to detect whether signal Clk is in-lock or out-of-lock with signal Vref. Lock-detect circuitry 20 includes, in part, a frequency comparator 22, a validation circuitry 24, a control logic 26 and a data acquisition block 28. Frequency comparator 22 compares the frequencies of signals Vref and Clk and generates a window (i.e., a pulse) whose width corresponds to a predetermined value. Validation circuitry receives the window generated by frequency comparator 22 and determines whether the frequency differential (i.e., offset) between signals Clk and Vref is greater or less than this window. If the offset between frequencies of signals Vref and Clk is less than the generated window, control logic block 26 generates a control signal to indicate that signal Clk is locked to signal Vref. The control signal generated by control logic 26 is applied to data acquisition block 28. After receiving this control signal, data acquisition block 28 switches to data acquisition mode at which point signal Clk is generated from an incoming data (not shown) and is again required to maintain lock to signal Vref.
Therefore, when lock-detect circuitry 20 switches to data acquisition mode, signal Clk despite being within the predetermined frequency range of signal Vref, may lose its lock as its frequency is now dependent on the frequency of the incoming data. If signal Clk loses its lock, lock-detect circuitry 20 switches from data acquisition mode back to frequency lock mode so as to enable signal CLK to reacquire its lock to signal Vref for a second time. The difference between frequencies of signals Vref and Clk during the second lock is often less than the difference between frequencies of these two signals during the first lock. However, signal Clk may lose its lock again. This second loss of lock may result, for example, from data jitter. The process of locking and unlocking may continue for some time until signal Clk acquires a frequency sufficiently close to that of signal Vref that it remains locked to signal Vref Prior art lock detectors, such as the one shown in FIG. 2, use the same window for detecting in-lock and out-of-lock conditions. Therefore, the detector may experience a number of in-lock and out-of-lock conditions before the detector acquires and maintains a stable lock. Furthermore, the windows used by prior art lock detectors are fixed and may not be selectively changed by the user.
A need continues to exist for a lock-detect circuitry adapted to more reliably lock the frequency of an incoming data signal to that of a reference clock signal.